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IC & MEMS packaging is
carried out
in various MIL-STD-1835C ceramic and
metal can packages viz. DIP, QFP, Gull-wing chip carrier, J-lead
chip carrier, PGA, TO-8 etc. Custom packages, as per application
requirements are developed for ASICs, electro-optical sensors and
MEMS devices. All the packaging processes are qualified as per the
requirements of MIL-PRF-38535 and the packaged devices tested to
meet the MIL-STD-883 requirements.
The Assembly and Packaging facility is housed in Class 1K/10k, ESD-safe
clean room area of about 5000 sq.ft. |
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PACKAGING PROCESS
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 Silicon wafers, glass-bonded silicon wafers and alumina
substrates
are diced
using hub-type and hub-less blades. The process
is carried out under a DI water jet. Wafers upto 150 mm diameter and
1.5 mm. thick are diced.
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 Die
attachment is done on ceramic packages, metal headers, PCB
and ceramic substrates. Silver-glass, conductive epoxy and
non-conductive epoxy processes are used depending on the application
requirement or type of package. Typical placement accuracy is
±
20
mm.
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 Al-wire
wedge bonding is done on ceramic packages, metal headers, PCB and
ceramic substrates. Gold-wire ball-bonding is also available for
Chip-on boards. Typically 1.25 mil bonding wire is being used and
devices with wire-counts upto 350 have been wire-bonded. The fully
automatic equipment can handle 500 wires of 0.7-1.5mil dia.
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Ceramic
packages
are hermetically sealed
in fully programmable thermal and IR furnaces.
Au-Sn eutectic and glass-frit sealing processes are used. KOVAR
headers and caps are hermetically sealed using Laser-welding
process. |
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ELECTRO-OPTICAL DEVICE PACKAGING
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 Special
processes have been developed, qualified for packaging of
electro-optical devices viz. 4K Linear Imager, Frame Transfer Imager
and TDI etc.
New materials have been identified and a low temperature process
developed to ensure low-stress die-attachment of large dies. Custom
equipment and tools have been developed to get placement accuracy
better than
±
10
mm.
A low temperature process is developed for hermetic sealing of AR
coated sapphire windows to the ceramic packages
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MEMS PACKAGING
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MEMS
devices are
packaged
using the same base-line processes as those
for CMOS device packaging in ceramic, Kovar and stainless steel packages.
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Following variants of the standard processes and packages are
developed to meet the MEMS specific applications such as:
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Retrofitting of standard dicing tools with customised
accessories for through-cut dicing of 675
mm
thick silicon wafers that are bonded to 1mm thick Pyrex glass.
Special techniques are also developed for wafer mounting and die
release.
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Special encapsulation techniques to protect the wire bonds while
the MEMS structure is exposed to the stimulus (pressure,
temperature, humidity etc.)
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New materials and processes for low temperature (125°C) sealing.
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Screen Printing of Thick Film Resistors on ceramic substrates.
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Laser Trimming of thick film resistors printed on ceramic
substrates.
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CHIP ON BOARD PACKAGING
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 Chip
on board (COB) technology delivers a cost effective solution for IC
packaging as it provides direct attachment of bare die to PCB. PCB
size could vary from 25 to 80 mm square. Products viz. Analog Watch
COBs, Hearing Aid, Digital Organiser etc. have been assembled in the
past. Some MEMS devices are also packaged using the COB
processes/packages. |
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