Micro-Electro-Mechanical Systems (MEMS)


MEMS Process


SCL has a state-of-the-art manufacturing facility for producing MEMS devices in 6” wafer size and has capability of design, fabrication, packaging and testing. The design activities are taken up for the development of RF MEMS, Temperature Sensor  and Peizoresistive Pressure sensor etc. Designers work closely with process engineers and produce production ready designs.

SCL’s MEMS  Fabrication line  includes the following  process technologies :

Surface micromachining
  Bulk Micromachining
  Substrate bonding (Eutectic and Anodic)
  Special Metal deposition
     
These technologies are built upon the unit processes developed on the CMOS Process line, such as
     
Thin Film Growth & Deposition
Lithography
  Etching
  Implantation

CMOS processes are carried out in the 6” VLSI Fab and Post CMOS Operations in Class-100 MEMS Fab. The protocols and facility planning ensure that there is no cross contamination.

Surface micromachining

Top

         
 

Process ID

Structural Layer

Sacrificial Layer

 

SNO

Silicon Nitride Silicon Dioxide
  SPO Poly Silicon Silicon Dioxide  
  SAO

Aluminum

Silicon Dioxide  
       


   
   
   
Double Poly process, with stress free Polysilicon structures
Vertical etch of structural layer through DRIE
Stiction free surface micromachining process
Good selectivity of etchant with Aluminum
  Option of using Gold metallization, for best selectivity with surface micromachining etchant
     
   
   
     
     
     
     
Bulk Micromachining

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Process ID

Micromachining Side Etch Stop  
BBE Back Side Electro Chemical Etch Stop  
BBT Back Side Timed Etch Stop  
BFT Front Side Timed Etch Stop  
BBD Back Side DRIE based process  
BFD Front Side DRIE based process  
 
       
 

 
       
  KOH (Wet) bulk micromachining :
    Silicon diaphragms upto 25μ thickness with Timed KOH process and upto 10μ  thickness,  using Electro-chemical etch stop process
    Protective coating and fixture used for protecting active side of the wafer during KOH etching
    Silicon Oxide- Nitride stack used as masking layer
  Deep Reactive Ion Etching (DRIE) :
    Vertical etching and through-and-through wafer etching  using DRIE Bosch process
    Photoresist and Silicon Oxide used as masking layer
     
Substrate Bonding Top
     
     
  Glass to Silicon substrate (Anodic bonding) and Silicon to Silicon wafer bonding (Eutectic Bonding)
  Upto three wafer stack ( Thickness < 2 mm)
  ≤ 2µ Alignment accuracy  using bottom side alignment system
  Vacuum (upto 5 x10-5 mBar) and Overpressure (< 2.5 bar, with Nitrogen ambient) bonding conditions possible
     
     
       
 

 
       
Special Metal deposition Top
     
  E- Beam Evaporation
  Deposition of  Cr, Au, Pt, Al and  Ti
  Lift-off and Non Lift-off processes  
  300Å to 10,000 Å thickness
  Uniformity better than ± 5%.
  Deposition rate up to 10Å/sec.